The present invention relates to a semiconductor memory device, and more particularly, to a low-current consumption semiconductor memory device having an input/output control circuit and a control method thereof.
Recently a number of studies have been undertaken to study different ways to obtain and to design low-current consumption semiconductor memory integrated circuits. Even though high-speed operation and high-level of integration are regarded as being highly desirable low-current consumption is also a desirable feature. Especially, this low-current consumption feature is very desirable in cases where the semiconductor memory device is used as a mobile component.
To reduce or minimize operating currents during active and precharge operations of a semiconductor memory device, it is very important to reduce current consumption during an input/output operations.
In this regard, FIG. 1 depicts a cell block diagram illustrating a typical semiconductor memory device. Here, the ‘S/A’ represents a sense amplifier, the ‘Cell Mat’ denotes a cell matrix, the ‘SWLD’ denotes a sub-wordline driver, the ‘S/H’ denotes a sub-hole, the ‘BISH’ and ‘BISL’ represent a bit line selection signal, the S/A Ctrl’ denotes a sense amplifier controller, the ‘Blk Ctrl’ denotes a block controller, and the ‘IOSW’ denotes an input/output switching signal.
FIG. 2 is a circuit diagram illustrating an input/output switch of a typical sub-hole. Furthermore, FIG. 3 is a circuit diagram illustrating a conventional input/output control circuit which controls input/output switch of FIG. 2.
When an arbitrary block address (for instance, block “1”) and an active command are received from the outside, an IOSW signal, which is a connecting transistor control signal between a local input/output line LIO/LIOb and a sub-input/output line SIO/SIOb to connect between a bit line sense amplifier BLSA and an input/output sense amplifier IOSA in the relevant cell block, is transitioned to a high level, thereby connecting a path between the bit line sense amplifier BLSA and the input/output sense amplifier IOSA, i.e., LIO/LIOb & SIO/SIOb, to each other.
In addition, when a precharge command is received, the bit line sense amplifier BLSA is precharged to a bit line precharge voltage VBLP and an IOSW signal, which is a local input/output line LIO/LIOb & sub-input/output line SIO/SIOb data line connecting transistor control signal, is transited to a logically low level, thereby blocking a path between the bit line sense amplifier BLSA and the input/output sense amplifier IOSA, i.e., a path (LIO/LIOb & SIO/SIOb).
As described above, whenever an active and precharge command is received, an input/output control signal IOSW is changed from the boosted voltage VPP to the ground voltage VSS, or from the ground voltage VSS level to the boosted voltage VPP, thereby generating a switching current consumption. For current consumption at a boosted voltage VPP stage, because the boosted voltage VPP is generated by pumping a supply voltage VDD with a VPP pump, pumping current of the VPP pump is also consumed, thereby further increasing current consumption on the whole.
The VPP pump efficiency is typically 25-30%, and thus overall current consumption becomes 3 to 4 times larger than the switching current of the input/output control signal IOSW.
However, according to an input/output control circuit having a structure shown in FIGS. 2 and 3, when an active & precharge command is received, regardless of the position of each cell array block shown in FIG. 1, it becomes a structure that the input/output control signal IOSW is unconditionally toggled. In that event, however, a large amount of current is consumed due to a toggle of the input/output control signal IOSW, and as a result low-current consumption operation cannot be achieved.